Method for fabricating semiconductor package

ABSTRACT

A semiconductor package and a method for fabricating the same are proposed. A substrate having a first circuit layer, a second circuit layer, and a core layer formed between the first and second circuit layers is provided. At least one second opening is formed on the second circuit layer. At least one first opening is formed on the first circuit layer corresponding to the second opening. A plurality of finger holes corresponding to bond fingers on the first circuit layer are formed in the core layer. A through opening is formed in the core layer and communicates with the first and second openings. At least one chip is mounted on the first circuit layer and covers the first opening, with its active surface being exposed to the first opening. An encapsulant is formed to fill the first and second openings and the through opening and encapsulate the chip.

FIELD OF THE INVENTION

The present invention relates to semiconductor packages and fabricationmethods thereof, and more particularly, to a window ball grid array(WBGA) semiconductor package with an improved yield, and a method forfabricating the semiconductor package.

BACKGROUND OF THE INVENTION

A window ball grid array (WBGA) semiconductor package employs anadvanced type of BGA packaging technology, wherein at least one openingis formed through a substrate, and a semiconductor chip is mounted onthe substrate in an upside-down manner that an active surface of thechip faces downwards and covers the opening of the substrate, allowingthe chip to be electrically connected to a lower surface of thesubstrate via a plurality of gold wires received in the opening. Suchpackage structure can effectively reduce the length of gold wires andimprove the quality of electrical communication between the chip andsubstrate, which thus has been widely applied to DRAM (dynamic randomaccess memory) chips having central pads.

U.S. Pat. No. 6,218,731 discloses a WBGA semiconductor package. As shownin FIG. 1, this semiconductor package 3 comprises a substrate 30 havinga central opening 304 therethrough; a chip 31 mounted on the substrate30, with bond pads 310 a on an active surface 310 of the chip 31 beingexposed to the opening 304 of the substrate 30; a plurality of goldwires 33 received in the opening 304, for electrically connecting thebond pad 310 a of the chip 31 to a lower surface of the substrate 30; afirst encapsulant 340 and a second encapsulant 341 formed on an uppersurface and the lower surface of the substrate 30 respectively, forencapsulating the chip 31 and filling the opening 304; a plurality ofsolder balls 35 implanted on the lower surface of the substrate 30 nothaving the second encapsulant 341, for establishing electricalconnection with external electronic devices.

Conventionally due to cost concerns for fabricating the abovesemiconductor package, a molding process is performed in a batch mannerto encapsulate a substrate strip comprising a plurality of substrates,and then a sawing process is carried out to separate apart theindividual substrates. As shown in FIG. 2, after the chip-mounting andwire-bonding processes, the substrate strip 30 (designated with the samereference numeral as substrate) is placed between an upper mold and alower mold of a transfer mold 37. After engaging the upper and lowermolds, injecting a molding compound and performing a curing step, whichare known in the art, the first encapsulant 340 and the secondencapsulant 341 are respectively formed on the upper surface and thelower surface of the substrate 30. Finally, after the ball-implantingprocess, the package structure is sawed to form a plurality ofindividual WBGA semiconductor packages 3.

Such molding method is relatively cost-effective and suitable for massproduction. However, since loops of the gold wires and the secondencapsulant for encapsulating the gold wires protrude from the lowersurface of the substrate, in order to fabricate appropriate secondencapsulants, it needs to prepare different types of molds correspondingto different sizes and structures of openings in the substrates, whichwould undesirably increase the fabrication cost. Moreover, in order tocompletely encapsulate the gold wires, the second encapsulant may occupyrelatively much area on the substrate, thereby limiting the density andnumber of solder balls that can be implanted on the substrate. Inaddition, since the first encapsulant and the second encapsulant are notcompletely symmetric to each other, the upper and lower molds may notfirmly clamp the substrate, thereby leading to flash of the secondencapsulant on the lower surface of the substrate. This not only affectsthe appearance of the package but also may cover ball pads on lowersurface of the substrate, which would adversely affect theball-implanting process and degrade the electrical performance of thesolder balls formed on the ball pads. As a result, an extra step ofusing a solvent to remove the encapsulant flash is required. The flashproblem is thus considered as a significant drawback in the prior art.

Therefore, the problem to be solved here is to provide a semiconductorpackage and a method for fabricating the same, which can increase thedensity of implanted solder balls and solve the flash problem, so as toimprove the overall yield and electrical performance.

SUMMARY OF THE INVENTION

Accordingly, a primary objective of the present invention is to providea semiconductor package and a method for fabricating the same, withouthaving an encapsulant protruding out of a substrate in the semiconductorpackage.

Another objective of the present invention is to provide a semiconductorpackage and a method for fabricating the same, which can increase thedensity of implanted solder balls on a substrate in the semiconductorpackage.

Still another objective of the present invention is to provide asemiconductor package and a method for fabricating the same, without theoccurrence of flash of an encapsulant.

A further objective of the present invention is to provide asemiconductor package and a method for fabricating the same, which onlyrequire the use of simple molds.

A further objective of the invention is to provide a semiconductorpackage and a method for fabricating the same, which can enhance themechanical strength and supportability of bonding wires in thesemiconductor package.

Another objective of the invention is to provide a semiconductor packageand a method for fabricating the same, which can improve the yield ofthe bonding wires and the electrical performance of the semiconductorpackage.

In order to achieve the foregoing and other objectives, the presentinvention proposes a method for fabricating a semiconductor package,comprising the steps of: preparing a substrate having a first circuitlayer, a second circuit layer, and a core layer formed between the firstcircuit layer and the second circuit layer; forming at least one secondopening on the second circuit layer, and forming at least one firstopening on the first circuit layer at a position corresponding to thesecond opening; forming a plurality of finger holes in the core layer atpositions corresponding to a plurality of bond fingers formed on thefirst circuit layer; forming a through opening in the core layer,allowing the through opening to communicate with the first opening ofthe first circuit layer and the second opening of the second circuitlayer; mounting at least one chip on the first circuit layer of thesubstrate, allowing the chip to cover the first opening and allowing anactive surface of the chip to be exposed to the first opening; forming aplurality of bonding wires to electrically connect the active surface ofthe chip to the plurality of bond fingers on the first circuit layerthrough the finger holes; forming an encapsulant on the substrate tofill the first and second openings and the through opening andencapsulate the chip and the bonding wires; and implanting a pluralityof solder balls on the substrate.

A semiconductor package fabricated by the above method according to thepresent invention comprises: a substrate having a first circuit layer, asecond circuit layer, and a core layer formed between the first circuitlayer and the second circuit layer, wherein at least one second openingis formed on the second circuit layer and at least one first opening isformed on the first circuit layer at a position corresponding to thesecond opening, and wherein a plurality of finger holes are formed inthe core layer at positions corresponding to a plurality of bond fingersformed on the first circuit layer, and a through opening is formed inthe core layer and communicates with the first and second openings; atleast one chip mounted on the first circuit layer of the substrate tocover the first opening, allowing an active surface of the chip to beexposed to the first opening; a plurality of bonding wires forelectrically connecting the active surface of the chip to the pluralityof bond fingers on the first circuit layer through the finger holes; anencapsulant for filling the first and second openings and the throughopening and encapsulating the chip and the bonding wires; and aplurality of solder balls implanted on the substrate.

The above finger holes in the core layer are formed by laser drilling.By a material selectivity characteristic of laser, the laser drillingtechnique can avoid damage to the bond fingers on the first circuitlayer. The through opening in the core layer is formed by using arouter. And the first opening of the first circuit layer and the secondopening of the second circuit layer are formed by a conventional etchingtechnique.

In addition, the core layer is further formed with a plurality ofconductive vias for electrically connecting the first and second circuitlayers to each other. A nickel (Ni)/gold (Au) layer is plated on thebond fingers respectively so as to enhance the bonding reliabilitybetween the bonding wires and the bond fingers.

Accordingly, by provision of the first and second openings of the firstand second circuit layers respectively and the plurality of finger holesin the core layer in the present invention, the bonding wires arecompletely received in the through opening of the substrate, such thatthe encapsulant for encapsulating the bonding wires does not protrudeout of the substrate. This allows the density of solder balls implantedon the substrate to be increased, and eliminates the drawbacks ofencapsulant flash and difficulty in standardizing the mold used forfabricating the encapsulant. Moreover, in the present invention, themechanical strength and supportability of the bonding wires can beimproved. Thus the problems in the prior art can be solved by thepresent invention.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention can be more fully understood by reading the followingdetailed description of the preferred embodiments with reference made tothe accompanying drawings, wherein:

FIG. 1 (PRIOR ART) is a schematic cross-sectional view of a WBGAsemiconductor package disclosed by U.S. Pat. No. 6,218,731;

FIG. 2 (PRIOR ART) is a flow chart showing a molding process and asawing process for fabricating conventional WBGA semiconductor packages;

FIGS. 3A to 3I are schematic diagrams showing procedural steps of amethod for fabricating a substrate used in a semiconductor packageaccording to the present invention; and

FIGS. 4A to 4D are schematic diagrams showing procedural steps of amethod for fabricating the semiconductor package according to thepresent invention using the substrate shown in FIG. 3I.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Preferred embodiments of a semiconductor package and a method forfabricating the same proposed in the present invention are described indetail as follows with reference to FIGS. 3A to 3I and FIGS. 4A to 4D,wherein FIGS. 3A to 3I show a fabrication method of a substrate used inthe semiconductor package.

First, referring to FIG. 3A, a dual-layer substrate 10, such as a copperclad laminate (CCL) substrate, is prepared. This substrate 10 comprisesa first copper circuit layer 100; a second copper circuit layer 101; aninsulating core layer 102 formed between the first and second circuitlayers 100, 101, making the first and second circuit layers 100, 101separated by the core layer 102; and a plurality of conductive vias 107formed in the core layer 102, for electrically connecting the first andsecond circuit layers 100, 101 to each other. Then, referring to FIG.3B, the first and second circuit layers 100, 101 are subjected to apatterning process including exposure, development, etching, etc. torespectively form predetermined circuit patterns. As a result, the firstcircuit layer 100 is formed with a plurality of bond fingers 104 and acentral first opening 100 a. The second circuit layer 101 is formed witha central second opening 101 a corresponding in position to the firstopening 100 a of the first circuit layer 100, wherein the first opening100 a is smaller than the second opening 101 a, and predeterminedportions of the core layer 102 are exposed via the first opening 100 aand the second opening 101 a. As shown in FIGS. 3B and 3C (FIG. 3C is atop view of FIG. 3B), the first opening 100 a is surrounded and definedby the plurality of bond fingers 104 of the first circuit layer 100, andthe second opening 101 a is surrounded and defined by conductive traces(not shown) of the second circuit layer 101.

Subsequently, referring to FIG. 3D, a solder mask 18 is applied on thefirst circuit layer 100 and the second circuit layer 101 respectively toprotect the circuit patterns thereof. A plurality of openings 180 areformed in the solder mask 18 covering the second circuit layer 101 toexpose predetermined portions of the circuit patterns of the secondcircuit layer 101.

Referring to FIG. 3E, a laser drilling technique is adopted to drill aplurality of finger holes 105 on the portion of the core layer 102exposed via the second opening 101 a of the second circuit layer 101,and the finger holes 105 correspond in position to the plurality of bondfingers 104 of the first circuit layer 100. The finger holes 105 aremade penetrating the core layer 102 such that the bond fingers 104 canbe partially exposed via the finger holes 105. This process isaccomplished by a material selectivity characteristic of laser to removeonly the material of core layer 102 without damaging the material ofbond fingers 104 by adjusting the energy of laser. As shown in FIG. 3F,which is a top view of FIG. 3E, areas with oblique lines in the fingerholes 105 represent the portions of the bond fingers 104 exposed via thefinger holes 105.

Referring to FIG. 3G, a plating process is performed to form a nickel(Ni)/gold (Au) layer 16 on the exposed portions of the bond fingers 104and a copper layer 103 of the circuit patterns exposed from the openings180 of the solder mask 18, so as to allow bonding wires and solder balls(not shown) to be subsequently bonded to the Ni/Au layer 16 that canenhance the bonding reliability. Referring to FIGS. 3H and 3I, a routeris used to form a through opening 102 a in the core layer 102, and thethrough opening 102 a communicates with the second opening 101 a of thesecond circuit layer 101 and the first opening 100 a of the firstcircuit layer 100. As shown in FIG. 3H, the through opening 102 a alsocommunicates with the finger holes 105, such that the subsequentlyformed bonding wires can electrically connect a chip (not shown) to thebond fingers 104 through the first opening 100 a, the through opening102 a and the finger holes 105 where the bond fingers 104 are exposed.This completes the fabrication of the substrate 10 in the presentinvention. FIG. 3I is a cross-sectional view of FIG. 3H taken along line3I-3I through the finger holes 105, which allows the relative sizes andlocations of the through opening 102 a and finger holes 105 to beobserved.

Accordingly, the above fabricated substrate 10 can be used to fabricatea semiconductor package according to the present invention by a methodillustrated in FIGS. 4A to 4D. In FIGS. 4A to 4D, the substrate 10 isturned upside down, that is to allow the first circuit layer 100 to faceupwards.

First, referring to FIG. 4A, an active surface 110 of a chip 11 ismounted via an adhesive 12 on the solder mask 18 covering the firstcircuit layer 100 of the substrate 10 in a manner that, the firstopening 100 a is covered by the chip 11, and bond pads 111 formed on thechip 11 are exposed to the first opening 100 a. Then, referring to FIG.4B, a wire-bonding process is performed to form a plurality bondingwires 13, such as gold wires, for electrically connecting the bond pads111 of the chip 11 to the bond fingers 104 on the first circuit layer100, wherein the bonding wires 13 are completely received in the throughopening 102 a of the substrate 10 and connected to the Ni/Au layer 16plated respectively on the bond fingers 104 through the finger holes 105where the bond fingers 104 are exposed (FIG. 3H); that is, the bondingwires 13 are inserted in the finger holes 105 to be connected to thebond fingers 104. The supportability of the bonding wires 13 is enhancedby the surrounding core layer 102, thereby improving the reliability andyield of the wire-bonding process. Referring to FIG. 4C, an encapsulant14 is formed on the substrate 10 to encapsulate the chip 11 and thebonding wires 13 and fill the through opening 102 a, the first andsecond opening 100 a, 101 a and the finger holes 105 of the substrate10. Since the bonding wires 13 are completely received in the throughopening 102 a, the encapsulant 14 for encapsulating the bonding wires 13does not protrude out of the substrate 10. In other words, the height ofthe encapsulant 14 filling the first and second openings 100 a, 101 aand the through opening 102 a is equal to or smaller than the thicknessof the substrate 10. This thus eliminates the prior-art problems ofencapsulant flash and limitation on density of solder balls arranged onthe substrate, and only requires a simple encapsulation mold, forexample comprising an upper mold with a cavity and a flat lower mold,for fabricating the encapsulant 14 in the present invention. Finally,referring to FIG. 4D, a plurality of solder balls 15 are implanted atthe Ni/Au layer 16 plated on the second circuit layer 101 of thesubstrate 10, and the overall structure is sawed to completely form thesemiconductor package according to the present invention.

Therefore, the semiconductor package in the present invention is shownin FIG. 4D, comprising: a substrate 10, at least one chip 11, aplurality of bonding wires 13, an encapsulant 14, and a plurality ofsolder balls 15.

The substrate 10 comprises a first circuit layer 100, a second circuitlayer 101, and a core layer 102 formed between the first circuit layer100 and the second circuit layer 101. At least one first opening 100 ais formed on the first circuit layer 100, and at least one secondopening 101 a is formed on the second circuit layer 101. A plurality offinger holes 105 are provided in the core layer 102 at positionscorresponding to a plurality of bond fingers 104 formed on the firstcircuit layer 100. A through opening 102 a is formed through the corelayer 102 and communicates with the first opening 100 a and the secondopening 101 a (FIG. 3I). The chip 11 is mounted via its active surface110 on the first circuit layer 100 of the substrate 10 in a manner that,the chip 11 covers the first opening 100 a, and a plurality of bond pads111 formed on the chip 11 are exposed to the first opening 100 a. Thebonding wires 13 electrically connect the bond pads 111 of the chip 11to the bond fingers 104 on the first circuit layer 100 through thefinger holes 105. The solder balls 15 are implanted on the secondcircuit layer 101 of the substrate 10 and can be electrically connectedto an external device such as a printed circuit board. The encapsulant14 encapsulates the chip 11 and the bonding wires 13 and fills thethrough opening 102 a, the first and second opening 100 a, 101 a and thefinger holes 105.

In summary, the semiconductor package and the method for fabricating thesame provided by the present invention allow the encapsulant not toprotrude out of the substrate, such that the density of solder ballsimplanted on the substrate can be increased, and the prior-art problemsof encapsulant flash and difficulty in standardizing the encapsulationmold are eliminated. Moreover, by provision of the finger holes with thesurrounding core layer, the mechanical strength and supportability ofthe bonding wires can be enhanced strengthened, thereby improving thereliability and yield of the wire bonding process as well as theelectrical performance of the semiconductor package.

The invention has been described using an exemplary preferredembodiment. However, it is to be understood that the scope of theinvention is not limited to the disclosed embodiments. On the contrary,it is intended to cover various modifications and similar arrangements.The scope of the claims, therefore, should be accorded the broadestinterpretation so as to encompass all such modifications and similararrangements.

1: A method for fabricating a semiconductor package, comprising thesteps of: preparing a substrate having a first circuit layer, a secondcircuit layer, and a core layer formed between the first circuit layerand the second circuit layer; forming at least one second opening on thesecond circuit layer, and forming at least one first opening on thefirst circuit layer at a position corresponding to the second opening;forming a plurality of finger holes in the core layer at positionscorresponding to a plurality of bond fingers formed on the first circuitlayer; forming a through opening in the core layer, allowing the throughopening to communicate with the first opening of the first circuit layerand the second opening of the second circuit layer; mounting at leastone chip on the first circuit layer of the substrate, allowing the chipto cover the first opening and allowing an active surface of the chip tobe exposed to the first opening; forming a plurality of bonding wires toelectrically connect the active surface of the chip to the plurality ofbond fingers on the first circuit layer through the finger holes; andforming an encapsulant on the substrate to fill the first and secondopenings and the through opening and encapsulate the chip and thebonding wires. 2: The method of claim 1, wherein the plurality ofbonding wires are inserted in the finger holes to be connected to thebond fingers. 3: The method of claim 1, wherein the through opening ofthe core layer communicates with the finger holes. 4: The method ofclaim 1, wherein the finger holes of the core layer are formed by laserdrilling. 5: The method of claim 1, wherein the through opening of thecore layer is formed by using a router. 6: The method of claim 1,wherein the first opening of the first circuit layer and the secondopening of the second circuit layer are formed by etching. 7: The methodof claim 1, wherein a nickel (Ni)/gold Au) layer is formed on the bondfingers respectively. 8: The method of claim 7, wherein the Ni/Au layeris formed by plating. 9: The method of claim 1, wherein the bondingwires are completely received in the through opening of the substrate.10: The method of claim 1, wherein the height of the encapsulant fillingthe first and second openings and the through opening is equal to orsmaller than the thickness of the substrate. 11: The method of claim 1,wherein the core layer is further formed with a plurality of conductivevias for electrically connecting the first and second circuit layers toeach other. 12: The method of claim 1, further comprising implanting aplurality of solder balls on the substrate. 13-20. (canceled)